First of all, of course, change the environment and reduce static electricity from the source (such as reducing friction, wearing less woolen sweaters, controlling air temperature and humidity, etc.). Of course, this is not the focus of our discussion today. When we are discussing today, how to involve the protection circuit in the circuit, when there is static electricity outside, our electronic components or systems can protect themselves from being damaged by static electricity (in fact, it is to install a lightning rod). This is also the number one problem for many IC designers and manufacturers. Many companies have teams that specialize in ESD design. Today I will explain to you the principles and points of attention of ESD protection from the most basic theory. You will find the PN mentioned earlier. Junction/diode, triode, MOS tube, all used...

When the previous topic explained the theory of PN junction diode, it was mentioned that the diode has a characteristic: forward conduction and reverse cutoff (if you don’t remember, go to the previous lesson), and the reverse bias voltage continues to increase, and an avalanche breakdown will occur. ) And turn on, we call it a clamp diode (Clamp). This is the theoretical basis that we need to design electrostatic protection. We are electrostatic discharge (ESD: Electrostatic Discharge), which should be the main culprit causing all electronic components or integrated circuit systems to cause excessive electrical stress (EOS: Electrical Over Stress) damage . Because static electricity usually has a very high instantaneous voltage (>several thousand volts), this kind of damage is devastating and permanent, and will cause the circuit to burn directly. Therefore, preventing electrostatic damage is the number one problem in all IC design and manufacturing.

Static electricity is usually generated by humans, such as production, assembly, testing, storage, handling, etc., it may cause static electricity to accumulate in the human body, instrument or equipment, and even the components themselves will also accumulate static electricity. Under the circumstance, contacting these charged objects will form a discharge path, instantly causing electronic components or systems to be damaged by electrostatic discharge (this is why in the past it was necessary to wear an electrostatic ring on the work table to prevent the human body from being damaged. Static electricity damages the chip), just as the charge stored in the cloud instantly penetrates the cloud to produce violent lightning, which will split the earth, and it is usually when the rain comes, because the air humidity is easy to form a conductive connection.

So, how to prevent electrostatic discharge damage? Use this reverse cut-off feature to make the bypass in a disconnected state during normal operation, and when there is static electricity from the outside, the bypass diode undergoes avalanche breakdown to form a bypass path to protect the internal circuit or gate (is it similar to a home? The sink has an overflow to prevent the faucet from being turned off and causing the entire bathroom to flood).

So the question is, will the protection circuit be completely dead if it breaks down? Is it a one-off?

The answer is of course no. The breakdown of PN junction is divided into two types, namely electrical breakdown and thermal breakdown. Electrical breakdown refers to avalanche breakdown (low concentration) and Zener breakdown (high concentration), and this electrical breakdown is mainly load Current collision ionization generates new electron-hole pairs, so it is recoverable. But thermal breakdown is irrecoverable, because heat buildup causes silicon (Si) to be melted and burned. Therefore, we need to control the current at the moment of turn-on. Generally, a high resistance is connected in series with the protection diode. In addition, can you draw inferences and understand why the ESD area cannot form Silicide? There is also a theory for everyone. ESD is usually next to the Pad at the input of the chip, not inside the chip, because we always hope that the external static electricity needs to be discharged as soon as possible. The chip PAD dissected earlier has diodes beside it. There are even two-level ESD to achieve the purpose of double protection.

Before talking about the principle and process of ESD, let's talk about the standards and test methods of ESD. According to the generation method of static electricity and the damage mode to the circuit, it is usually divided into four test methods: Human-Body Model (HBM: Human-Body Model) ), machine discharge mode (Machine Model), component charging mode (CDM: Charge-Device Model), electric field induction mode (FIM: Field-Induced Model), but the industry usually uses the first two modes for testing (HBM, MM).

Human body model (HBM)

Of course, the charge generated by the friction of the human body suddenly hits the chip and the charge released causes the chip to burn and break down. This is the reason why you often get an electric shock when you touch other people in the fall. The industry also has traces to the HBM ESD standard (MIL-STD-883C method 3015.7, equivalent human body capacitance is 100pF, equivalent human body resistance is 1.5Kohm), or international electronic industry standards (EIA/JESD22-A114-A) Regulations, depending on which one you want to follow. If it is MIL-STD-883C method 3015.7, it stipulates that those less than 2kV are Class-1, those with 2kV~4kV are class-2, and those with 4kV~16kV are class-3.

Machine discharge mode (MM)

Of course, the static electricity generated by the movement of a machine (such as a robot) is released by the pin when it touches the chip. The substandard is EIAJ-IC-121 method 20 (or standard EIA/JESD22-A115-A), and the equivalent machine resistance is 0 (because Metal), the capacitance is still 100pF. Since the machine is made of metal and the resistance is 0, the discharge time is very short, almost between ms or us. But the more important problem is that because the equivalent resistance is 0, the current is very large, so even the 200V MM discharge is more harmful than the 2kV HBM discharge. In addition, the machine itself has many wires that can be coupled to each other, so the current will change with time and interfere with the change.

The ESD test method is similar to the GOI test in FAB. After specifying the pin, give him an ESD voltage. After a period of time, then come back and test the electrical properties to see if it is damaged. If there is no problem, add a step of ESD voltage and continue for a period of time. After time, the electrical properties are measured again, and the process is repeated until breakdown. At this time, the breakdown voltage is the ESD failure threshold voltage (ESD failure threshold Voltage). Usually we apply the voltage to the circuit three times (3 zaps). In order to reduce the test cycle, usually the initial voltage is 70% ESD threshold of the standard voltage, and each step can be adjusted by 50V or 100V according to the needs.

(1). Stress number = 3 Zaps. (5 Zaps, the worst case)

(2). Stress step

ΔVESD = 50V(100V) for VZAP <=1000V
ΔVESD = 100V(250V, 500V) for VZAP > 1000V

(3). Starting VZAP = 70% of averaged ESD failure threshold (VESD)

In addition, because each chip has a lot of pins, whether you are testing a pin or a combination of pins, it will be divided into several combinations: I/O-pin test (Input and Output pins), pin-to-pin test, Vdd-Vss test (input terminal to output terminal), Analog-pin.

1. I/O pins

It is to do ESD test on input-pin and output-pin separately, and the charge is positive and negative, so there are four combinations: input+positive charge, input+negative charge, output+positive charge, output+negative charge. When testing input, output and other pins are all floating (floating), and vice versa.

2.pin-to-pin test

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

3. Electrostatic discharge between Vdd-Vss

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

In addition, because each chip has a lot of pins, whether you are testing a pin or a combination of pins, it will be divided into several combinations: I/O-pin test (Input and Output pins), pin-to-pin test, Vdd-Vss test (input terminal to output terminal), Analog-pin.

1. I/O pins

It is to do ESD test on input-pin and output-pin separately, and the charge is positive and negative, so there are four combinations: input+positive charge, input+negative charge, output+positive charge, output+negative charge. When testing input, output and other pins are all floating (floating), and vice versa.

2.pin-to-pin test

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

3. Electrostatic discharge between Vdd-Vss

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

In addition, because each chip has a lot of pins, whether you are testing a pin or a combination of pins, it will be divided into several combinations: I/O-pin test (Input and Output pins), pin-to-pin test, Vdd-Vss test (input terminal to output terminal), Analog-pin.

1. I/O pins

It is to do ESD test on input-pin and output-pin separately, and the charge is positive and negative, so there are four combinations: input+positive charge, input+negative charge, output+positive charge, output+negative charge. When testing input, output and other pins are all floating (floating), and vice versa.

2.pin-to-pin test

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

3. Electrostatic discharge between Vdd-Vss

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

In addition, because each chip has a lot of pins, whether you are testing a pin or a combination of pins, it will be divided into several combinations: I/O-pin test (Input and Output pins), pin-to-pin test, Vdd-Vss test (input terminal to output terminal), Analog-pin.

1. I/O pins

It is to do ESD test on input-pin and output-pin separately, and the charge is positive and negative, so there are four combinations: input+positive charge, input+negative charge, output+positive charge, output+negative charge. When testing input, output and other pins are all floating (floating), and vice versa.

2.pin-to-pin test

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).

3. Electrostatic discharge between Vdd-Vss

Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test too many combinations every two pins, because any I/O voltage will affect the entire circuit, you must first go through VDD/Vss. It supplies power to the entire circuit, so the improved version uses a certain I/O-pin to add a positive or negative ESD voltage, all other I/Os are grounded together, but the input and output are floating at the same time (Floating).